Performance Evaluation of Gate-Driven and Body-Driven MOS-Based Transimpedance Amplifiers

Sharroush, Sherif Moustafa; Shaban, Aya; Abdalla, Yasser; Nafea, Sherif

doi:10.21608/pserj.2024.251637.1289

Performance Evaluation of Gate-Driven and Body-Driven MOS-Based Transimpedance Amplifiers

Document Type : Original Article

Authors

¹ Electrical-Engineering Department, Faculty of Engineering, Port Said University, Port Said, Egypt.

² Department of Computer Engineering and Networks College of Computer and Information Sciences, Jouf University and Faculty of Technology and Education Suez University

³ Department of Electrical Engineering, Faculty of Engineering, Suez Canal University Ismailia, Egypt

10.21608/pserj.2024.251637.1289

Abstract

In this paper, a comparative examination of four various transimpedance amplifier (TIA) topologies is performed. Each of the four topologies is precisely designed to fit a diverse range of applications. The discussed topologies are the common source (CS) with resistive feedback, the regulated cascode (RGC), the CMOS inverter with resistive feedback, and the composite cascode with resistive feedback. Each topology was studied in both gate-driven (GD) and body-driven (BD) configurations with a thorough evaluation of its performance characteristics provided. Among these topologies, the composite cascode topology is proposed for use for the first time with TIAs in both the gate-driven and the body-driven configurations. The type of applications that are suitable for specific performance metrics are mentioned. The simulation is performed utilizing 130-nm CMOS technology predictive technology model (PTM) with a power-supply voltage, VDD, of 1.2 V for GD configurations and 0.9 V for BD configurations. Finally, the impact of technology scaling on the performance of the GD and BD configurations are investigated.

Keywords